High Speed & Low Power Comparator Designs for Flash ADC


  • E. Chandrasekhar, K. Ramanjaneyulu


In this paper the design of low power arm latch comparator for 4 bit flash ADC was presented. The 4 bit Flash ADC required 15(2N-1) comparators and a thermometer code word to binary code encoder. The major issue in the design of Flash ADC is the large power consumption because of the large number of comparators used in it. So in order to reduce the power consumption of a Flash ADC, we have design a comparator with very low power consumption. Different comparators are designed and their power consumptions are observed. The comparator with lowest power consumption is selected. All comparators are designed and simulated in CMOS 180nm and 45nm technology. The schematic of the all circuits are design with cadence virtuoso.